SN65LVDS32PWR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS32PWR
Manufacturer

TI
ChipWorker Part#

CW58404524
Category

Interface IC, Interface Controller
Package

TSSOP-16
Description

TEXAS INSTRUMENTS SN65LVDS32PWR Differential Line Receiver IC, LVDS, 400Mbps, 4 Receivers, 8kV ESD, 3V to 3.6V, TSSOP-16
Documentation

Datasheet

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SN65LVDS32PWR Specifications

Attribute	Attribute Value

Part Number	SN65LVDS32PWR
Manufacturer	TI
ChipWorker Part#	CW58404524
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Voltage (DC)	3.00V (min)
Power Dissipation	774 mW
Input Voltage (Max)	0.1 V
Input Current (Min)	20 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	774 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15

Product Description

DESCRIPTION
The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are differential line receivers
that implement the electrical characteristics of low-voltage differential signaling (LVDS). This
signaling technique lowers the output voltage levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input
common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.
FEATURES
• Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
• Operate With a Single 3.3-V Supply
• Designed for Signaling Rates of up to 100 Mbps (See Table 1)
• Differential Input Thresholds ±100 mV Max
• Typical Propagation Delay Time of 2.1 ns
• Power Dissipation 60 mW Typical Per Receiver at Maximum Data Rate
• Bus-Terminal ESD Protection Exceeds 8 kV
• Low-Voltage TTL (LVTTL) Logic Output Levels
• Pin Compatible With AM26LS32, MC3486, and μA9637
• Open-Circuit Fail-Safe
• Cold Sparing for Space and High Reliability Applications Requiring Redundancy

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