SN74HC164PW ,Shift Register IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

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133 points

Part No

SN74HC164PW
Manufacturer

TI
ChipWorker Part#

CW13905439
Category

Shift Register IC
Package

TSSOP-14
Description

TEXAS INSTRUMENTS SN74HC164PW Shift Register, HC Family, 74HC164, Serial to Parallel, 1Element, 8Bit, TSSOP, 14Pins
Documentation

Datasheet
Ships from

Moscow
Наличие

4228 pcs In Stock
Estimated Price

$ 0.68

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SN74HC164PW Specifications

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Attribute	Attribute Value

Part Number	SN74HC164PW
Manufacturer	TI
ChipWorker Part#	CW13905439
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	TSSOP-14
Frequency	28 MHz
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	8 Output
Number of Circuits	1 Circuit
Number of Positions	14 Position
Number of Bits	8 Bit
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Output Current Drive	-1.00 mA
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
	expand all
Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	Yes
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

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Product Description

The SN74HC164PW is a 8-bit parallel-out serial Shift Register features AND-gated serial inputs and an asynchronous clear (CLR\\) input. The gated serial (A and B) inputs permit complete control over incoming data, a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. clocking occurs on the low-to-high-level transition of CLK.
Outputs can drive up to 10 LSTTL loads
80µA Maximum low power consumption
Typical tpd = 20ns
±4mA Output drive at 5V
1µA Maximum low input current
AND-gated (enable/disable) serial inputs
Fully buffered clock and serial inputs
Direct clear
Green product and no Sb/Br

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