SN74HC165PW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74HC165PW
Manufacturer

TI
ChipWorker Part#

CW12556536
Category

Shift Register IC
Package

TSSOP-16
Description

Shift Register, 74HC165, Parallel to Serial, Serial to Serial, 1Element, 8Bit, TSSOP, 16Pins
Documentation

Datasheet

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SN74HC165PW Specifications

Attribute	Attribute Value

Part Number	SN74HC165PW
Manufacturer	TI
ChipWorker Part#	CW12556536
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Frequency	29 MHz
Supply Voltage (DC)	2.00V ~ 6.00V
Operating Voltage	2V ~ 6V
Number of Outputs	1 Output
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	30.0 ns
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Output Current Drive	-1.00 mA
Number of Inputs	9 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99

Product Description

The SN74HC165PW is a 8-bit parallel-load Shift Register that when clocked shift the data toward a serial (QH) output. The parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD\\) input. This device also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output. clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. parallel loading is inhibited when SH/LD\ is held high. While SH/LD\ is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH or serial (SER) inputs.
Outputs can drive up to 10 LSTTL loads
Complementary outputs
Direct overriding load (data) inputs
Gated clock inputs
Parallel-to-serial data conversion
80µA Maximum low power consumption
13ns Typical tpd
±4mA Output drive at 5V
1µA Maximum low input current
Green product and no Sb/Br

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