SN74HC259N ,Latche IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

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132 points

Part No

SN74HC259N
Manufacturer

TI
ChipWorker Part#

CW9999485
Category

Latche IC
Package

PDIP-16
Description

8Bit Addressable Latches 16-PDIP -40℃ to 85℃
Documentation

Datasheet
Ships from

Moscow
Наличие

In Stock
Estimated Price

$ 0.28

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SN74HC259N Specifications

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Attribute	Attribute Value

Part Number	SN74HC259N
Manufacturer	TI
ChipWorker Part#	CW9999485
Category	Latche IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	8 Output
Output Current	5.2 mA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	28.0 ns
Polarity	Non-Inverting
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Output Current Drive	-1.00 mA
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

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Product Description

The SN74HC259N is a 8-bit Addressable Latch designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers and active-high decoders or demultiplexers. It is multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear (CLR)\ and enable (G)\ inputs. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G\ should be held high (inactive) while the address lines are changing.
High-current inverting outputs drive up to 10 LSTTL loads
8-bit Parallel-out storage register performs serial-to-parallel conversion with storage
Asynchronous parallel clear
Active-high decoder
Enable input simplifies expansion
Expandable for n-bit applications
Four distinct functional modes
80µA Maximum low power consumption
14ns Typical tpd
±4mA Output drive at 5V
1µA Maximum low input current
±20mA Input and output clamp current
±25mA Continuous output current
±50mA Continuous current through VCC or GND

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