SN74HC573APWR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74HC573APWR
Manufacturer

TI
ChipWorker Part#

CW249244
Category

Latche IC
Package

TSSOP-20
Description

Latch Transparent 3-ST 8CH D-Type 20Pin TSSOP T/R
Documentation

Datasheet

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SN74HC573APWR Specifications

Attribute	Attribute Value

Part Number	SN74HC573APWR
Manufacturer	TI
ChipWorker Part#	CW249244
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	TSSOP-20
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	8 Output
Output Current	7.8 mA
Number of Circuits	8 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	38.0 ns
Polarity	Non-Inverting
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Output Current Drive	-1.00 mA
Number of Inputs	8 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	6.5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74HC573APWR is an octal transparent D Latch with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor.
High-current 3-state outputs drive bus lines directly or up to 15 LSTTL loads
Bus-structured pinout
80µA Maximum low power consumption
21ns Propagation delay (typical)
±6mA Output drive at 5V
1µA Maximum low input current
Green product and no Sb/Br

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