SN74LS377N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LS377N
Manufacturer

TI
ChipWorker Part#

CW3594037
Category

Flip Flop IC
Package

DIP-20
Description

TEXAS INSTRUMENTS SN74LS377N Flip-Flop, with Clock Enable, Non Inverted, Positive Edge, 74LS377, D, 17ns, 40MHz, 8mA, DIP
Documentation

Datasheet

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SN74LS377N Specifications

Attribute	Attribute Value

Part Number	SN74LS377N
Manufacturer	TI
ChipWorker Part#	CW3594037
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	20 Pin
Case/Package	DIP-20
Frequency	40 MHz
Digital Logic Level	TTL
Supply Voltage (DC)	4.75V ~ 5.25V
Number of Outputs	8 Output
Output Current	8 mA
Supply Current	17.0 mA
Number of Circuits	8 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Clock Speed	40 MHz
Number of Bits	8 Bit
Propagation Delay Max (tpd)	27.0 ns
Polarity	Non-Inverting
Voltage Nodes	5.00 V
Output Current Drive	-50.0 µA
Number of Inputs	8 Input
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.75V ~ 5.25V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	4.75 V
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Size-Length	24.33 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LS377N is an octal D-type Flip-flop with clock enable. It utilizes TTL circuitry to implement D-type flip-flop logic with an enable input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input. It is guaranteed to respond to clock frequencies ranging from 0 to 30MHz while maximum clock frequency is typically 40MHz. Typical power dissipation is 10mW per flip-flop.
Individual data input to each flip-flop
TTL Input and output

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