SN74LV595AD - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LV595AD
Manufacturer

TI
ChipWorker Part#

CW8794196
Category

Shift Register IC
RoHS

Lead free / RoHS Compliant
Description

TEXAS INSTRUMENTS SN74LV595AD Shift Register, LV Family, 74LV595, Serial to Parallel, 1Element, 8Bit, SOIC, 16Pins
Documentation

Datasheet

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SN74LV595AD Specifications

Attribute	Attribute Value

Part Number	SN74LV595AD
Manufacturer	TI
ChipWorker Part#	CW8794196
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC-16
Frequency	170 MHz
Supply Voltage (DC)	2.00V ~ 5.50V
Number of Outputs	9 Output
Number of Positions	16 Position
Number of Bits	8 Bit
Voltage Nodes	5.00 V, 3.30 V, 2.50 V
Output Current Drive	-1.00 mA
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2 V
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Size-Length	9.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LV595AD is a 8-bit serial-in parallel-out Shift Register feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for the shift and storage registers. The shift register has a direct overriding clear (SRCLR\\) input, serial (SER) input and serial outputs for cascading. When the OE\ input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. This low-drive CMOS device can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The inputs are 5V tolerant allowing for down translation to VCC.
Support mixed-mode voltage operation on all ports
Ioff Supports live insertion, partial power-down mode and back-drive protection
Shift register has direct clear
Latch-up performance exceeds 250mA per JESD 17
Green product and no Sb/Br

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