SN74LVC16374ADGGR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC16374ADGGR
Manufacturer

TI
ChipWorker Part#

CW5921096
Category

Flip Flop IC
Package

TSSOP-48
Description

TEXAS INSTRUMENTS SN74LVC16374ADGGR Flip-Flop, Tri State Non Inverted, Positive Edge, 74LVC163, D, 4.5ns, 150MHz, 24mA, TSSOP
Documentation

Datasheet

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SN74LVC16374ADGGR Specifications

Attribute	Attribute Value

Part Number	SN74LVC16374ADGGR
Manufacturer	TI
ChipWorker Part#	CW5921096
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	TSSOP-48
Frequency	150 MHz
Supply Voltage (DC)	1.65V ~ 3.60V
Number of Outputs	16 Output
Output Current	24 mA
Number of Circuits	8 Circuit
Number of Channels	16 Channel
Clock Speed	150 MHz
Number of Bits	16 Bit
Propagation Delay Max (tpd)	4.50 ns
Polarity	Non-Inverting
Voltage Nodes	3.30 V
Input Capacitance	5 pF
Output Current Drive	-1.00 mA
Number of Inputs	8 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.65 V
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Size-Length	12.6 mm
Size-Width	6.2 mm
Size-Height	1.05 mm
Weight	0.0035711329652 kg
Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

The SN74LVC16374ADGGR is a 16-bit edge-triggered D-type Flip-flop with 3-state outputs. It is designed for 1.65 to 3.6V VCC operation. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. On the positive transition of the clock input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered OE input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Ioff Supports live insertion, partial-power-down mode and back-drive protection
Supports mixed-mode signal operation on all ports
Latch-up performance exceeds 250mA per JESD 17
Green product and no Sb/Br

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