SN74LVC1G374DCKR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC1G374DCKR
Manufacturer

TI
ChipWorker Part#

CW22627351
Category

Flip Flop IC
Package

SC-70-6
Description

Flip Flop D-Type Pos-Edge 3-ST 1Element 6Pin SC-70 T/R
Documentation

Datasheet

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SN74LVC1G374DCKR Specifications

Attribute	Attribute Value

Part Number	SN74LVC1G374DCKR
Manufacturer	TI
ChipWorker Part#	CW22627351
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	6 Pin
Case/Package	SC-70-6
Frequency	175 MHz
Supply Voltage (DC)	1.65V (min)
Number of Outputs	1 Output
Number of Circuits	1 Circuit
Number of Positions	6 Position
Clock Speed	175 MHz
Number of Bits	1 Bit
Propagation Delay Max (tpd)	3.00 ns
Polarity	Non-Inverting
Number of Gates	1 Gate
Input Capacitance	3 pF
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Length	2 mm
Size-Width	1.25 mm
Size-Height	0.9 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC1G374DCKR is a single D-type Flip-flop designed for 1.65 to 5.5V VCC operation. It features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers and working registers. On the positive transition of the clock input, the Q output is set to the logic level set up at the data (D) input. A buffered OE\ input can be used to place the output in either a normal logic state or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Supports down translation to VCC
Ioff Supports live insertion, partial-power-down mode and back-drive protection
Latch-up performance exceeds 100mA per JESD 78, class II
10µA Maximum low power consumption
±24mA Output drive at 3.3V
Green product and no Sb/Br

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