SN74LVTH244APW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVTH244APW
Manufacturer

TI
ChipWorker Part#

CW6169093
Category

Logic Controller, Logic IC
Package

TSSOP-20
Description

3.3V ABT Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40℃ to 85℃
Documentation

Datasheet

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SN74LVTH244APW Specifications

Attribute	Attribute Value

Part Number	SN74LVTH244APW
Manufacturer	TI
ChipWorker Part#	CW6169093
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	TSSOP-20
Supply Voltage (DC)	2.70V ~ 3.60V
Number of Outputs	8 Output
Output Current	64 mA
Number of Channels	8 Channel
Number of Positions	20 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	3.50 ns
Voltage Nodes	3.30 V, 2.70 V
Static Current	5.00 mA
Number of Gates	8 Gate
Output Current Drive	-500 µA
Output Current (Max)	64 mA
Number of Inputs	8 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.7V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.7 V
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Size-Length	6.5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVTH244APW is an octal Buffer/Line Driver designed specifically for low-voltage (3.3V) VCC operation, but with the capability to provide a TTL interface to a 5V system environment. It is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the devices pass data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. It is fully specified for hot-insertion applications using IOFF and power-up 3-state. The IOFF circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
Support mixed-mode signal operation
IOFF and power-up 3-state support hot insertion
Bus hold on data inputs eliminates the need for external pull-up/pull-down resistors
Support unregulated battery operation down to 2.7V
Latch-up performance exceeds 500mA per JESD 17
<0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
Green product and no Sb/Br

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