TPIC6B595DW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TPIC6B595DW
Manufacturer

TI
ChipWorker Part#

CW10953133
Category

Shift Register IC
Package

SOIC-20
Description

IC: peripheral circuit; 8Bit, shift register; SMD; SO20-W; 90ns; 5Ω
Documentation

Datasheet

TPIC6B595DW Global Supplier

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TPIC6B595DW Specifications

Attribute	Attribute Value

Part Number	TPIC6B595DW
Manufacturer	TI
ChipWorker Part#	CW10953133
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	SOIC-20
Frequency	5 kHz
Supply Voltage (DC)	4.50V (min)
Power Rating	1389 mW
Number of Outputs	9 Output
Output Voltage	≤50.0 V
Output Current	500 mA
Supply Current	20.0 µA
Number of Circuits	1 Circuit
Number of Positions	20 Position
Number of Bits	8 Bit
Power Dissipation	1.39 W
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
	expand all
Size-Width	7.52 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

The TPIC6B595DW is a 8-bit Shift Register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids and other medium current or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift-register clear (SRCLR\\) is high. When SRCLR\ is low, the input shift register is cleared. When output enable (G\\) is held high, all data in the output buffers is held low and all drain outputs are off. When G\ is held low, data from the storage register is transparent to the output buffers.
Eight power DMOS transistor outputs of 150mA continuous current
Can be Cascadable
Low power consumption
5R Typical low rDS(on)
30mJ Avalanche energy
50V Output clamp voltage
Green product and no Sb/Br

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