TPIC6C595N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TPIC6C595N
Manufacturer

TI
ChipWorker Part#

CW7363979
Category

Shift Register IC
RoHS

Lead free / RoHS Compliant
Description

Shift Register, Serial to Parallel, 1Element, 8Bit, DIP, 16Pins
Documentation

Datasheet

TPIC6C595N Global Supplier

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TPIC6C595N Specifications

Attribute	Attribute Value

Part Number	TPIC6C595N
Manufacturer	TI
ChipWorker Part#	CW7363979
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Supply Voltage (DC)	4.50V (min)
Number of Outputs	9 Output
Output Voltage	≤33.0 V
Output Current	100 mA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Drain to Source Resistance (on) (Rds)	7.00 mΩ
Number of Bits	8 Bit
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
	expand all
Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99

Product Description

The TPIC6C595N is a 8-bit Shift Register designed for use in systems that require relatively moderate load power such as LEDs. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids and other low-current or medium-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The device transfers data out the serial output (SER OUT) port on the rising edge of SRCK. The storage register transfers data to the output buffer when shift register clear (CLR\\) is high. When CLR\ is low, the input shift register is cleared. When output enable (G\\) is held high, all data in the output buffers is held low and all drain outputs are off.
Eight power DMOS transistor outputs of 100mA continuous current
Cascadable
Low power consumption
250mA Current limit capability
2500V ESD Protection
30mJ Avalanche energy

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