Z85C3008VSG - Zilog

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

Z85C3008VSG
Manufacturer

Zilog
ChipWorker Part#

CW18428509
Category

Interface IC, Interface Controller
Package

PLCC-44
Description

ZILOG Z85C3008VSG Specialized Interface, Serial, Data Communication Equipment, 4.5V, 5.5V, LCC, 44Pins
Documentation

Datasheet

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Z85C3008VSG Specifications

Attribute	Attribute Value

Part Number	Z85C3008VSG
Manufacturer	Zilog
ChipWorker Part#	CW18428509
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	44 Pin
Case/Package	PLCC-44
Frequency	8 MHz
Supply Voltage (DC)	5.00 V
Supply Current	9.00 mA
Number of Positions	44 Position
Clock Speed	8.00 MHz
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Size-Length	16.66 mm
Size-Width	16.66 mm
Size-Height	3.86 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The Z85C3008VSG is a Serial Communications Controller (SCC) with dual-channel, multiprotocol data communications peripheral that easily interfaces with CPU"s with either multiplexed or non-multiplexed address/data buses. It is a pin and software compatible CMOS member of the SCC family introduced by Zilog in 1981. The advanced CMOS process offers lower power consumption, higher performance and superior noise immunity. The programming flexibility of the internal registers allows the SCC to be configured to various serial communications applications. The many on-chip features such as baud rate generators (BRG), digital phase locked loops (DPLL) and crystal oscillators reduce the need for an external logic. Additional features include a 10 x 19-bit status FIFO and 14-bit byte counter to support high speed SDLC transfers using DMA controllers.
Improve functionality to ease sending back-to-back frames
Automatic SDLC opening flag transmission
Automatic Tx underrun/EOM latch reset in SDLC mode
Automatic RTS deactivation
TxD Pin forced high in SDLC NRZI mode after closing flag
Complete CRC reception
Improved response to abort sequence in status FIFO
Automatic Tx CRC generator preset/reset
Extended read for write registers
Write data set-up timing improvement
Programmable DTR/REQ timing
Write data to falling edge of WR setup time requirement is now eliminated
Reduced INT timing
Extended read function to read back the written value to the Write registers
Latching RRO during read

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