AD6649 - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD6649
Manufacturer

ADI
ChipWorker Part#

CW622310870
Description

IF Diversity Receiver IF sampling frequencies to 400MHz
Documentation

Datasheet

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AD6649 Specifications

Attribute	Attribute Value

Part Number	AD6649
Manufacturer	ADI
ChipWorker Part#	CW622310870
Documentation	Datasheet
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Product Lifecycle Status	Recommended for New Designs

Product Description

Product Details
The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.
In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.
The AD6649 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-pin SPI-compatible serial interface.
The AD6649 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
**APPLICATIONS**
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
General-purpose software radios
Broadband data applications
**PRODUCT HIGHLIGHTS**
1. Integrated dual, 14-bit, 250 MSPS ADC.
2. Integrated wideband decimation filter and 32-bit complex NCO.
3. Fast overrange and threshold detect.
4. Proprietary differential input maintains excellent SNR performance for input frequencies up to 300 MHz.
5. SYNC input allows synchronization of multiple devices.
6. 3-pin, 1.8V SPI port for register programming and register readback.
### Features and Benefits
SNR = 73.0 dBFS in a 95 MHz BW at 185 MHz Ain and
245.76 MSPS
SFDR = 85 dBc at 185 MHz Ain and 250 MSPS
-151.2 dBFS/Hz Input Noise @ 220 MHz, -1dBFS Ain and 250MSPS
Total Power consumption: 1W
1.8 V analog and LVDS output supply operation
Integer 1-to-8 input clock divider (625Mhz maximum input)
Integrated dual-channel ADC
\-- Sample rates up to 250 MSPS
\-- IF sampling frequencies to 400 MHz
Integrated wideband digital downconverter (DDC)
\-- 32-bit complex, numerically controlled oscillator (NCO)
\-- Sample Rate Converter and FIR filter with two modes
\-- Real Output from an fs/4 output NCO
Fast detect bits for efficient AGC implementation
Energy-saving power-down modes
Decimated Interleaved ‘Real’ LVDS Data Outputs
\-- See datasheet for additional features

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