AD9511BCPZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9511BCPZ
Manufacturer

ADI
ChipWorker Part#

CW404739
Category

Clock Buffer, Driver, PLL IC
Package

LFCSP-48
Description

Clock Fanout Buffer 5Out 2IN 1:5 48Pin LFCSP EP Tray
Documentation

Datasheet

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AD9511BCPZ Specifications

Attribute	Attribute Value

Part Number	AD9511BCPZ
Manufacturer	ADI
ChipWorker Part#	CW404739
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	LFCSP-48
Frequency	1.2 GHz
Supply Voltage (DC)	3.13V (min)
Number of Outputs	5 Output
Number of Circuits	1 Circuit
Number of Positions	48 Position
Clock Speed	800 MHz
Power Dissipation	0.85 W
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3.135V ~ 3.465V
Supply Voltage (Max)	3.465 V
Supply Voltage (Min)	3.135 V
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Size-Height	0.83 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

Product Details
The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Three independent LVPECL and two LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz.
The PLL section consists of a programmable reference divider, R; a low-noise phase frequency detector, PFD; a precision charge pump, CP; and a programmable feedback divider, N. By connecting an external VCXO or VCO to the CLK2 and CLK2B pins, PLL output frequencies up to 1.6 GHz may be synchronized to the input reference, REFIN.
The clock distribution section provides LVPECL outputs and outputs that may be programmed to either LVDS or CMOS. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.
Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. One output also features a programmable delay element with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.
The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.
The AD9511 is available in a 48-lead LFCSP and is specified from -40°C to +85°C. The part may be run from a single 3.3 V supply. Users wishing to extend the voltage range for external VCOs may run the charge pump supply, VCP, to 5.5V.
**Applications**
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE™ Converters
Wireless infrastructure transceivers
High performance instrumentation
Broadband infrastructure
### Features and Benefits
Phase locked loop (PLL) Core
Reference input frequencies to 250 MHz
Programmable dual-modulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCP) extends tuning range
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
Three independent 1.2 GHz LVPECL outputs
Additive output jitter , 225 fs RMS
Two independent 800 MHz/250 MHz LVDS/CMOS outputs
Additive output jitter, 275 fs RMS
Fine delay adjust on one output, 5-bit delay words
4-wire or 3-wire serial control port
Space-saving 48-lead LFCSP

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