ADF4156 - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

ADF4156
Manufacturer

ADI
ChipWorker Part#

CW543101625
Description

6.2GHz Fractional-N Frequency Synthesizer
Documentation

Datasheet

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ADF4156 Specifications

Attribute	Attribute Value

Part Number	ADF4156
Manufacturer	ADI
ChipWorker Part#	CW543101625
Documentation	Datasheet
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Product Lifecycle Status	Active

Product Description

Product Details
The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer that implements local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a ∑∆ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.
**Applications**
* CATV equipment
* Base stations for mobile radio (WiMAX, GSM, PCS, DCS, SuperCell 3G, CDMA, WCDMA)
* Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
* Wireless LANs, PMR
* Communications test equipment
### Features and Benefits
RF bandwidth to 6.2 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the ADF4110, ADF4111, ADF4112, ADF4113, ADF4106, ADF4153, and ADF4154 frequency synthesizers
Programmable RF output phase
Loop filter design possible with ADIsimPLL
Cycle slip reduction for faster lock times

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