AM3352BZCZA60 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AM3352BZCZA60
Manufacturer

TI
ChipWorker Part#

CW10122630
Category

Microprocessor IC
Package

PBGA-324
Description

MPU AM335x RISC 32Bit 600MHz 1.8V/3.3V 324Pin NFBGA
Documentation

Datasheet

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AM3352BZCZA60 Specifications

Attribute	Attribute Value

Part Number	AM3352BZCZA60
Manufacturer	TI
ChipWorker Part#	CW10122630
Category	Microprocessor IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	324 Pin
Case/Package	PBGA-324
Frequency	600 MHz
Number of Positions	324 Position
Number of UARTs	6 UART
Operating Temperature (Max)	105 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	1.378 V
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Operating Temperature	-40℃ ~ 105℃ (TJ)
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
HK STC License	NLR

Product Description

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Linux® and Android™ are available free of charge from TI.
The AM335x microprocessor contain the subsystems shown in Figure 1-1 and a brief description of each follows:
The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.
The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

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