CD4021BE - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD4021BE
Manufacturer

TI
ChipWorker Part#

CW670683
Category

Shift Register IC
Package

PDIP-16
Description

Shift Register, CD4021, Parallel to Serial, Serial to Serial, 1Element, 8Bit, DIP, 16Pins
Documentation

Datasheet

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CD4021BE Specifications

Attribute	Attribute Value

Part Number	CD4021BE
Manufacturer	TI
ChipWorker Part#	CW670683
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Digital Logic Level	CMOS
Supply Voltage (DC)	15.0 V, 18.0 V (max)
Operating Voltage	3V ~ 18V
Number of Outputs	3 Output
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Voltage Nodes	5.00 V, 10.0 V, 15.0 V
Power Dissipation	500 mW
Input Capacitance	5 pF
Number of Inputs	9 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	3V ~ 18V
Supply Voltage (Max)	18 V
Supply Voltage (Min)	3 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Weight	0.015227096868 kg
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The CD4021BE is a CMOS 8-stage parallel or serial-input/serial output Static Shift Register with common clock and parallel/serial control inputs, a single serial data input and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output form stage 8, "Q" outputs are also available from stages 6 and 7. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. In both types, entry is controlled by the parallel/serial control input. When parallel/serial control input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the parallel/serial control input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BE, the clock input of the internal stage is "forced" when asynchronous parallel entry is made.
Medium speed operation
Fully static operation
8 Master-slave flip-flops plus output buffering and control gating
100% Tested for quiescent current at 20V
Maximum input current of 1µA at 18V
Standardized, symmetrical output characteristics

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