CD74AC138M ,Logic Controller, Logic IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

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176 points

Part No

CD74AC138M
Manufacturer

TI
ChipWorker Part#

CW4458608
Category

Logic Controller, Logic IC
Package

SOIC-16
Description

TEXAS INSTRUMENTS CD74AC138M Decoder / Demultiplexer, AC Family, 1 Gate, 3Input, 8 Output, 24mA, 1.5V to 5.5V, SOIC-16
Documentation

Datasheet
Ships from

Moscow
Наличие

149078 pcs In Stock
Estimated Price

$ 0.07

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CD74AC138M Specifications

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Attribute	Attribute Value

Part Number	CD74AC138M
Manufacturer	TI
ChipWorker Part#	CW4458608
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC-16
Supply Voltage (DC)	1.50V (min)
Number of Outputs	8 Output
Number of Circuits	2 Circuit
Number of Channels	1 Channel
Number of Positions	16 Position
Number of Bits	32 Bit
Power Dissipation	725 mW
Number of Gates	1 Gate
Bandwidth	100 MHz
Number of Inputs	3 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	1.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.5 V
	expand all
Size-Length	9.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Weight	0.0022670548152 kg
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	Yes
REACH SVHC Compliance Edition	2015/06/15

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Product Description

The CD74AC138M is a 3-to 8 inverting Decoder/Demultiplexer designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Speed of bipolar F, AS and S, with significantly reduced power consumption
Designed specifically for high-speed memory decoders and data-transmission systems
Incorporate three enable inputs to simplify cascading and/or data reception
Balanced propagation delays
SCR Latchup-resistant CMOS process and circuit design
±24mA Output drive current
Green product and no Sb/Br

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