CD74HC40103E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC40103E
Manufacturer

TI
ChipWorker Part#

CW29453461
Category

Logic Controller, Logic IC
Package

PDIP-16
Description

TEXAS INSTRUMENTS CD74HC40103E Binary Synchronous Down Counter, HC Family, 25MHz, 2V to 6V, DIP-16
Documentation

Datasheet

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CD74HC40103E Specifications

Attribute	Attribute Value

Part Number	CD74HC40103E
Manufacturer	TI
ChipWorker Part#	CW29453461
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	1 Output
Number of Positions	16 Position
Clock Speed	25 MHz
Number of Bits	8 Bit
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Number of Inputs	8 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HC40103E is an 8-stage CMOS Synchronous Down Counter manufactured with high speed silicon gate technology and consist of a single output which is active when the internal count is zero. The 40103 contains a single 8-bit binary counter. Each has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. All control inputs and the TC\ output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the clock. Counting is inhibited when the TE\ input is high. The TC\ output goes low when the count reaches zero if the TE\ input is low and remains low for one full clock period. When the PE\ input is low, data at the P0-P7 inputs are clocked into the counter on the next positive clock transition regardless of the state of the TE\ input.
Cascadable in synchronous or ripple mode
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS Input compatibility
10 LSTTL Load standard outputs
15 LSTTL Loads bus driver outputs

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