CD74HCT193E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HCT193E
Manufacturer

TI
ChipWorker Part#

CW14888404
Category

Counter, Counter IC
Package

DIP-16
Description

TEXAS INSTRUMENTS CD74HCT193E Binary Synchronous Up / Down Counter, HCT Family, 22MHz, 4.5V to 5.5V, DIP-16
Documentation

Datasheet

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CD74HCT193E Specifications

Attribute	Attribute Value

Part Number	CD74HCT193E
Manufacturer	TI
ChipWorker Part#	CW14888404
Category	Counter, Counter IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Supply Voltage (DC)	4.50V ~ 5.50V
Number of Outputs	4 Output
Number of Positions	16 Position
Clock Speed	22 MHz
Number of Bits	4 Bit
Voltage Nodes	5.00 V
Number of Inputs	4 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HCT193E is a 4-bit high speed CMOS presettable synchronous Binary Up/Down Counter with asynchronous reset. Presetting the counter to the number on the preset data inputs (P0 to P3) is accomplished by a low asynchronous parallel load input (PL\\). The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count and returns to high at the maximum count.
Two outputs for n-bit cascading
Look-ahead carry for high-speed counting
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS Input compatibility
10 LSTTL Load standard outputs
15 LSTTL Load bus driver outputs

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