CDCE949PW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCE949PW
Manufacturer

TI
ChipWorker Part#

CW23604254
Category

Clock Chip, Timing IC
Package

TSSOP-24
Description

Clock Generator 8MHz to 160MHz Input 230MHz Output 24Pin TSSOP Tube
Documentation

Datasheet

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CDCE949PW Specifications

Attribute	Attribute Value

Part Number	CDCE949PW
Manufacturer	TI
ChipWorker Part#	CW23604254
Category	Clock Chip, Timing IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	24 Pin
Case/Package	TSSOP-24
Frequency	160 MHz
Supply Voltage (DC)	1.80 V
Number of Outputs	9 Output
Supply Current	38 mA
Number of Circuits	1 Circuit
Duty Cycle	60% (Max)
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.7V ~ 1.9V
Supply Voltage (Max)	1.9 V
Supply Voltage (Min)	1.7 V
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Size-Width	4.4 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.
The CDCEx949 has separate output supply pins, VDDOUT, 1.8 V for the CDCEL949, and 2.5 V to 3.3 V for CDCE949.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio or video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27 MHz.
All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.
The device supports non-volatile EEPROM programming for easy customization of the device to the application. It is preset to a factory-default configuration. It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.
The CDCEx949 operates in a 1.8-V environment. It operates within a temperature range of –40°C to 85°C.

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