CDCVF2310PW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CDCVF2310PW
Manufacturer

TI
ChipWorker Part#

CW4238044
Category

Clock Buffer, Driver, PLL IC
Package

TSSOP-24
Description

Clock Fanout Buffer 10Out 1IN 1:10 24Pin TSSOP Tube
Documentation

Datasheet

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CDCVF2310PW Specifications

Attribute	Attribute Value

Part Number	CDCVF2310PW
Manufacturer	TI
ChipWorker Part#	CW4238044
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	24 Pin
Case/Package	TSSOP-24
Frequency	200 MHz
Supply Voltage (DC)	3.30 V
Number of Outputs	10 Output
Supply Current	80.0 µA
Number of Circuits	1 Circuit
Number of Positions	24 Position
Clock Speed	200 MHz
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	2.3 V
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Size-Length	7.8 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
ECCN Code	EAR99
HK STC License	NLR

Product Description

The CDCVF2310PW is a high-performance low-skew Clock Buffer operates up to 200MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y(0:4) or 2Y(0:4) can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y(0:4) or 2Y(0:4) can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5 and 3.3V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.
High-performance 1:10 clock driver
Operates up to 200MHz at VDD 3.3V
Output Enable Glitch Suppression
Distributes one clock input to two banks of five outputs
25R On-chip series damping resistors
<100ps at VDD 3.3V Pin-to-pin skew
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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