EPM570GM100C5N - Altera

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

EPM570GM100C5N
Manufacturer

Altera
ChipWorker Part#

CW75072992
Category

CPLD chip
Package

BGA-100
Description

CPLD MAX II Family 440 Macro Cells 201.1MHz 0.18um Technology 1.8V 100Pin Micro FBGA
Documentation

Datasheet

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EPM570GM100C5N Specifications

Attribute	Attribute Value

Part Number	EPM570GM100C5N
Manufacturer	Altera
ChipWorker Part#	CW75072992
Category	CPLD chip
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	100 Pin
Case/Package	BGA-100
Frequency	201.1 MHz
Supply Voltage (DC)	1.80 V
Number of I/O Pins	76 IO
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	1.8 V
Supply Voltage (Max)	1.89 V
Supply Voltage (Min)	1.71 V
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Size-Height	0.85 mm
Operating Temperature	0℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
ECCN Code	EAR99
HK STC License	NLR

Product Description

* Low-cost, low-power CPLD * Instant-on, non Volatile architecture * Standby current as low as 25 μA * Provides fast propagation delay and clock-to-output times * Provides four global clocks with two clocks available per logic array block (LAB) * UFM block up to 8 Kbits for non Volatile storage * MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V * MultiVolt I/O interface supporting 3.3 V, 2.5 V, 1.8 V, and 1.5 V logic levels * Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors * Schmitt triggers enabling noise tolerant inputs (programmable per pin) * I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3 V operation at 66 MHz * Supports hot-socketing * Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 * ISP circuitry compliant with IEEE Std. 1532 * 440 Typical Equivalent Macrocells

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