HEF4520BT - NXP

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

HEF4520BT
Manufacturer

NXP
ChipWorker Part#

CW142829217
Category

Counter, Counter IC
Package

SOIC
Description

IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4Bit UP BINARY COUNTER, PDSO16, 3.9MM, PLATIC, SOT109-1, MS-012, SOP-16, Counter
Documentation

Datasheet

HEF4520BT Global Supplier

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HEF4520BT Specifications

Attribute	Attribute Value

Part Number	HEF4520BT
Manufacturer	NXP
ChipWorker Part#	CW142829217
Category	Counter, Counter IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC
Supply Voltage (DC)	4.50V (min)
Number of Positions	16 Position
Clock Speed	40 MHz
Number of Gates	2 Gate
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage (Max)	15.5 V
Supply Voltage (Min)	4.5 V
	expand all
Size-Length	10 mm
Size-Width	4 mm
Size-Height	1.45 mm
Product Lifecycle Status	Unknown
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17

Product Description

The HEF4520BT is a 4-bit dual internally synchronous Binary Counter has an active high clock input (nCP0) and an active low clock input (nCP1\\), buffered outputs from all four bit positions (nQ0 to nQ3) and an active high overriding asynchronous master reset input (nMR). The counter advances on either the low-to-high transition of the nCP0 input if nCP1\ is high or the high-to-low transition of the nCP1\ input if nCP0 is low. Either nCP0 or nCP1\ may be used as the clock input to the counter while the other clock input may be used as a clock enable input. Schmitt trigger action makes the clock input highly tolerant of slower clock rise and fall times. A high on nMR resets the counter (nQ0 to nQ3 = low) independent of nCP0 and nCP1\\. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.
Tolerant of slow clock rise and fall time
Fully static operation
Standardized symmetrical output characteristics
Complies with JEDEC standard JESD 13-B

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