ISO721MD - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

ISO721MD
Manufacturer

TI
ChipWorker Part#

CW10039540
Category

Interface Isolator, Digital Isolator
Package

SOIC-8
Description

TEXAS INSTRUMENTS ISO721MD Digital Isolator, 1Channel, 16ns, 3V, 5.5V, SOIC, 8Pins
Documentation

Datasheet

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ISO721MD Specifications

Attribute	Attribute Value

Part Number	ISO721MD
Manufacturer	TI
ChipWorker Part#	CW10039540
Category	Interface Isolator, Digital Isolator
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	3.30 V, 5.00 V
Rise/Fall Time	1 ns
Output Current	≤4.00 mA
Supply Current	10.0 mA
Number of Channels	1 Channel
Number of Positions	8 Position
Power Dissipation	195 mW
Data Rate	150 Mbps
Rise Time	2 ns
Isolation Voltage	2500 Vrms
Thermal Shutdown	No
Input Current (Min)	10 μA
Maximum Forward Voltage (Max)	5.5 V
Fall Time (Max)	2 ns
Fall Time (Max)	2 ns
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	195 mW
Supply Voltage	3V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	3 V
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Size-Length	5 mm
Size-Width	4 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The ISO721MD is a single channel Digital Isolator with a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000VPK per VDE. Used in conjunction with isolated power supplies, it prevents noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is assumed to be unpowered or not being actively driven and the failsafe circuit drives the output to a logic-high state.
Low propagation delay
Low pulse skew
Low-power sleep mode
High electromagnetic immunity (EMI)
Low input-current requirement
Failsafe output
Drop-in replacement for most opto and magnetic isolators
50kV/µs Typical transient immunity
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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