SN65LVDS93AZQLR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS93AZQLR
Manufacturer

TI
ChipWorker Part#

CW23990530
Category

Interface IC, Interface Controller
Package

BGA-56
Description

Flat Panel Display Link Serializer/Deserializer 135Mbps 1.8V/2.5V/3.3V 56Pin BGA MICROSTAR JUNIOR T/R
Documentation

Datasheet

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SN65LVDS93AZQLR Specifications

Attribute	Attribute Value

Part Number	SN65LVDS93AZQLR
Manufacturer	TI
ChipWorker Part#	CW23990530
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	56 Pin
Case/Package	BGA-56
Number of Outputs	4 Output
Supply Current	102.2 mA
Number of Inputs	28 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.62 V
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Size-Length	7 mm
Size-Width	4.5 mm
Size-Height	0.75 mm
Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	EAR99

Product Description

The SN65LVDS93A LVDS SerDes (serializer/deserializer) transmitter contains four 7-bit parallel load serial-out shift registers, a 7 × clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These functions allow synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94 (SLLS928).
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected through the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93A device requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the users. The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input and the possible use of the shutdown/clear (SHTDN) signal. SHTDN is an active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers at a low level.
The SN65LVDS93A is characterized for operation over ambient air temperatures of 40°C to 85°C.

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