SN65MLVD204AD - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65MLVD204AD
Manufacturer

TI
ChipWorker Part#

CW34331746
Category

Interface IC, Interface Controller
Package

SOIC-8
Description

M-LVDS PHY (<500Mbps) Half-Duplex M-LVDS Transceiver Single Transmitter/Receiver RS-899 8Pin SOIC Tube
Documentation

Datasheet

SN65MLVD204AD Global Supplier

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SN65MLVD204AD Specifications

Attribute	Attribute Value

Part Number	SN65MLVD204AD
Manufacturer	TI
ChipWorker Part#	CW34331746
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	3.00V (min)
Supply Current	16 mA
Number of Positions	8 Position
Power Dissipation	94 W
Data Rate	100 Mbps
Output Current (Max)	24 mA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	4.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	5A991.b.1

Product Description

The SN65MLVD204AD is a half-duplex multipoint low-voltage differential (M-LVDS) Line Driver and Receiver optimized to operate at signalling rates up to 100Mbps. All parts comply with the multipoint low-voltage differential signalling (M-LVDS) standard TIA/EIA-899. The SN65MLVD20xx device has enhancements over their predecessors. Improved features include controlled slew rate on the driver output to help minimize reflections from unterminated stubs, which results in better signal integrity. Additionally, 8kV ESD protection on the bus pins for more robustness. The same footprint definition was maintained making for an easy drop-in replacement for a system performance upgrade.
Low-voltage differential 30 to 55R line driver and receivers for signalling rate up to 100Mbps
Up to 50MHz clock frequency
Receivers provide an offset (100mV) threshold to detect open-circuit and idle-bus conditions
Meets or exceeds the M-LVDS standard TIA/EIA-899 for multipoint data interchange
Controlled driver output voltage transition times for improved signal quality
Bus pins high impedance when disabled or VCC
-1 to 3.4V Common-mode voltage range allows data transfer with 2V of ground noise
Green product and no Sb/Br

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