SN74AUP1G74DCUR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AUP1G74DCUR
Manufacturer

TI
ChipWorker Part#

CW2500627
Category

Flip Flop IC
Package

VSSOP-8
Description

TEXAS INSTRUMENTS SN74AUP1G74DCUR Flip-Flop, Complementary, Positive Edge, 74AUP1G74, D, 2ns, 200MHz, 20mA, VSSOP
Documentation

Datasheet

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SN74AUP1G74DCUR Specifications

Attribute	Attribute Value

Part Number	SN74AUP1G74DCUR
Manufacturer	TI
ChipWorker Part#	CW2500627
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	VSSOP-8
Frequency	200 MHz
Supply Voltage (DC)	-500 mV to 4.60 V
Number of Outputs	1 Output
Output Current	20 mA
Number of Circuits	1 Circuit
Number of Channels	1 Channel
Number of Positions	8 Position
Clock Speed	100 MHz
Number of Bits	1 Bit
Propagation Delay Max (tpd)	2.00 ns
Polarity	Non-Inverting
Input Capacitance	1.5 pF
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	0.8V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	0.8 V
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Size-Length	2.3 mm
Size-Width	2 mm
Size-Height	0.85 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74AUP1G74DCUR is a single positive-edge-triggered D-type Flip-flop designed for 0.8 to 3.6V VCC operation. A low level at the preset (PRE\\) or clear (CLR\\) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. When both the CLR\ and PRE\ inputs are set low, the CLR\ input will override the PRE\ input. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Low noise - Overshoot and undershoot <10% of VCC
Ioff Supports partial-power-down mode operation
Schmitt-trigger action allows slow input transition and better switching noise immunity
Suitable for point-to-point applications
Latch-up performance exceeds 100mA per JESD 78, Class II
3.6V I/O Tolerant to support mixed-mode signal operation
5ns at 3.3V Maximum tpd
0.9µA Maximum low static-power consumption
5.5pF Typical low dynamic-power consumption
1.5pF Typical low input capacitance
Green product and no Sb/Br

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