SN74HC166N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74HC166N
Manufacturer

TI
ChipWorker Part#

CW6227903
Category

Shift Register IC
Package

PDIP-16
Description

8Bit Parallel-Load Shift Registers 16-PDIP -40℃ to 85℃
Documentation

Datasheet

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SN74HC166N Specifications

Attribute	Attribute Value

Part Number	SN74HC166N
Manufacturer	TI
ChipWorker Part#	CW6227903
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Frequency	45 MHz
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	1 Output
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Output Current Drive	-1.00 mA
Number of Inputs	9 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Weight	0.015227096868 kg
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99

Product Description

The SN74HC166N is a 8-bit parallel-load Shift Register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR\\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\\) input. When high, SH/LD\ enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each CLK pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking, holding either low enables the other clock input. This allows the system clock to be free running and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
Outputs can drive up to 10 LSTTL loads
Typical tpd = 13ns
Synchronous load
Direct overriding clear
Parallel-to-serial conversion
80µA Maximum low power consumption
±4mA Output drive at 5V
1µA Maximum low input current

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