SN74LV8154N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LV8154N
Manufacturer

TI
ChipWorker Part#

CW25134658
Category

Logic Controller, Logic IC
Package

DIP-20
Description

TEXAS INSTRUMENTS SN74LV8154N Binary Counter, LV Family, 40MHz, 2V to 5.5V, DIP-20
Documentation

Datasheet

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SN74LV8154N Specifications

Attribute	Attribute Value

Part Number	SN74LV8154N
Manufacturer	TI
ChipWorker Part#	CW25134658
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	20 Pin
Case/Package	DIP-20
Supply Voltage (DC)	2.00V ~ 5.50V
Number of Outputs	8 Output
Number of Positions	20 Position
Clock Speed	40 MHz
Number of Bits	16 Bit
Voltage Nodes	5.00 V, 3.30 V, 2.50 V
Output Current Drive	-1.00 mA
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LV8154N is a 16-bit dual Binary Counter with 3-state output registers. It is designed for 2 to 5.5V VCC operation. It has dedicated clock inputs. The counter shares a clocked storage register to sample and save the counter contents. Both counters share an asynchronous clear input. The 32-bit storage register can be mapped on the output bus 8-bits at a time. Four bus reads are needed to access the contents of both stored counts. The two counters can be chained by connecting CLKBEN\ to RCOA\\. All clocks are positive edge triggered. All other inputs are active low. It is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Can be used as two 16-bit counters or a single 32-bit counter
Ioff Supports partial-power-down mode operation
Latch-up performance exceeds 250mA per JESD 17
8-bit Counter read bus

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