TMS320VC5409PGE100 - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TMS320VC5409PGE100
Manufacturer

TI
ChipWorker Part#

CW69031644
Category

DSP, Digital Signal Processor
Package

LQFP-144
Description

DSP Fixed-Point 16Bit 100MHz 100MIPS 144Pin LQFP DSP Fixed-Point 16Bit 100MHz 100MIPS 144Pin LQFP
Documentation

Datasheet

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TMS320VC5409PGE100 Specifications

Attribute	Attribute Value

Part Number	TMS320VC5409PGE100
Manufacturer	TI
ChipWorker Part#	CW69031644
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	144 Pin
Case/Package	LQFP-144
Frequency	100 MHz
Supply Voltage (DC)	1.71V (min)
Number of Positions	144 Position
Clock Speed	100 MHz
RAM Memory Size	64 KB
Number of Bits	16 Bit
Number of Inputs and Outputs	8 Input IO
Operating Temperature (Max)	100 ℃
Operating Temperature (Min)	-40 ℃
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Operating Temperature	-40℃ ~ 100℃
Product Lifecycle Status	Obsolete
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	3A991.a.2
HK STC License	NLR

Product Description

Introduction
The TMS320VC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5409 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
TMS320VC5409 Features
• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
• 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
• Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
• Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
• Data Bus With a Bus-Holder Feature
• Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
• 16K x 16-Bit On-Chip ROM
• 32K x 16-Bit Dual-Access On-Chip RAM
• Single-Instruction-Repeat and Block-Repeat Operations for Program Code
• Block-Memory-Move Instructions for Better Program and Data Management
• Instructions With a 32-Bit Long Word Operand
• Instructions With Two- or Three-Operand Reads
• Arithmetic Instructions With Parallel Store and Parallel Load
• Conditional Store Instructions
• Fast Return From Interrupt
• On-Chip Peripherals
− Software-Programmable Wait-State Generator and Programmable Bank Switching
− On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
− Three Multichannel Buffered Serial Ports (McBSPs)
− Enhanced 8-Bit Parallel Host-Port Interface With 16-Bit Data/Addressing
− One 16-Bit Timer
− Six-Channel Direct Memory Access (DMA) Controller
• Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
• CLKOUT Off Control to Disable CLKOUT
• On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† (JTAG) Boundary Scan Logic
• 12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS) for 3.3-V Power Supply (1.8-V Core)
• 10-ns Single-Cycle Fixed-Point Instruction Execution Time (100 MIPS) for 3.3-V Power Supply (1.8-V Core)
• Available in a 144-Pin Plastic Thin Quad Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)

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