TPIC6C596N ,Shift Register IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Popularity Score

88 points

Part No

TPIC6C596N
Manufacturer

TI
ChipWorker Part#

CW3983496
Category

Shift Register IC
Package

PDIP-16
Description

TEXAS INSTRUMENTS TPIC6C596N Shift Register, Serial to Parallel, 1Element, 8Bit, DIP, 16Pins
Documentation

Datasheet
Ships from

Moscow
Наличие

In Stock
Estimated Price

$ 0.59

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TPIC6C596N Specifications

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Attribute	Attribute Value

Part Number	TPIC6C596N
Manufacturer	TI
ChipWorker Part#	CW3983496
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	4.50V (min)
Number of Outputs	8 Output
Output Voltage	33 V
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
	expand all
Size-Width	6.35 mm
Weight	0.015227096868 kg
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

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Product Description

The TPIC6C596N is a 8-bit Shift Register designed for use in systems that require relatively moderate load power such as LEDs. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids and other low-current or medium-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (CLR\\) is high. When CLR\ is low, all registers in the device are cleared. When output enable (G\\) is held high, all data in the output buffers is held low and all drain outputs are off. When G\ is held low, data from the storage register is transparent to the output buffers.
Enhanced cascading for multiple stages
All registers cleared with single input
Low power consumption
Eight power DMOS transistor outputs of 100mA continuous current
30mJ Avalanche Energy
250mA Current limit capability
2500V ESD protection
33V Output Clamp Voltage

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