AD9139BCPZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

AD9139BCPZ
Manufacturer

ADI
ChipWorker Part#

CW1614263
Category

Digital to Analog, DAC IC
Package

LFCSP-72
Description

ANALOG DEVICES AD9139BCPZ Digital to Analogue Converter, 16Bit, 1.6GSPS, Parallel, Serial, 3.13V to 3.47V, LFCSP, 72Pins
Documentation

Datasheet

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AD9139BCPZ Specifications

Attribute	Attribute Value

Part Number	AD9139BCPZ
Manufacturer	ADI
ChipWorker Part#	CW1614263
Category	Digital to Analog, DAC IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	72 Pin
Case/Package	LFCSP-72
Number of Outputs	1 Output
Supply Current	400 µA
Number of Channels	1 Channel
Number of Positions	72 Position
Number of Bits	16 Bit
Sample Rate	1.60 GHz
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	3.13V ~ 3.47V
	expand all
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

Product Details
The AD9139 is an 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum update rate of 1600 MSPS, permitting multicarrier generation up to the Nyquist frequency. The AD9139 TxDAC+® includes features optimized for wide band communications applications, including 1× and 2× interpolation, a DLL based high speed interface, sample error detection, and parity detection. A 3-wire serial port interface provides for the programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA up to 33 mA. The AD9139 is available in a 72-lead LFCSP.
**Product Highlights**
1. 575 MHz achievable input signal bandwidth.
2. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
3. Very small inherent latency variation simplifies both software
and hardware design in the system. It allows easy multichip
synchronization for most applications.
4. Low power architecture improves power efficiency.
**APPLICATIONS**
Wireless communications: 3G/4G and MC-GSM base stations,
wideband repeaters, software defined radios
Wideband communications: point-to-point, LMDS/MMDS
Transmit diversity/MIMO
Instrumentation
Automated test equipment
### Features and Benefits
Selectable 1×, 2× interpolation filter
Support input signal bandwidth up to 575 MHz
Very small inherent latency variation: <2 DAC clock cycles
Proprietary low spurious and distortion design
6-carrier GSM ACLR = 79 dBc
at 200 MHz IF
SFDR > 85 dBc (bandwidth = 300 MHz) at Zero IF
Flexible 16-bit LVDS interface
Supports word and byte load
Multiple chip synchronization
Fixed latency and data generator latency compensation
FIFO eases system timing and includes error detection
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power:
700 mW at 1230 MSPS
72-lead LFCSP

expand all

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- Carefully tested and packaged by ChipWorker
- Vacuum packed
- Anti-static packaging
- Anti-vibration foam
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- X-ray inspection
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- Electrical testing
- Surface testing

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