ADF4193BCPZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

ADF4193BCPZ
Manufacturer

ADI
ChipWorker Part#

CW9332040
Category

Clock Generator IC
Package

LFCSP-32
Description

Clock Generator 300MHz to 3.5GHz Input 470MHz Output 32Pin LFCSP EP Tray
Documentation

Datasheet

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ADF4193BCPZ Specifications

Attribute	Attribute Value

Part Number	ADF4193BCPZ
Manufacturer	ADI
ChipWorker Part#	CW9332040
Category	Clock Generator IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	32 Pin
Case/Package	LFCSP-32
Frequency	3.50 GHz
Supply Voltage (DC)	2.70V (min)
Number of Outputs	1 Output
Supply Current	30 mA
Number of Circuits	1 Circuit
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.7V ~ 3.3V
Supply Voltage (Max)	3.3 V
Supply Voltage (Min)	2.7 V
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Size-Length	5.1 mm
Size-Width	5.1 mm
Size-Height	0.75 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Contains Lead
ECCN Code	EAR99

Product Description

Product Details
The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).
The Σ-Δ-based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures.
**Applications**
GSM/EDGE base stations
PHS base stations
Instrumentation and test equipment
### Features and Benefits
New, fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 µs with phase settled by 20 µs
0.5° rms phase error at 2 GHz RF output
Digitally programmable output phase
RF input range up to 3.5 GHz
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: –216 dBc/Hz
Loop filter design possible using ADIsimPLL™
Qualified for automotive applications

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