CD74HC273E ,Flip Flop IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Popularity Score

149 points

Part No

CD74HC273E
Manufacturer

TI
ChipWorker Part#

CW13542311
Category

Flip Flop IC
Package

DIP-20
Description

TEXAS INSTRUMENTS CD74HC273E Flip-Flop, with Reset, Non Inverted, Positive Edge, 74HC273, D, 12ns, 60MHz, 5.2mA, DIP
Documentation

Datasheet
Ships from

Moscow
Наличие

In Stock
Estimated Price

$ 1.02

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CD74HC273E Specifications

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Attribute	Attribute Value

Part Number	CD74HC273E
Manufacturer	TI
ChipWorker Part#	CW13542311
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	20 Pin
Case/Package	DIP-20
Frequency	60 MHz
Supply Voltage (DC)	5.00 V, 6.00 V (max)
Number of Outputs	8 Output
Output Current	5.2 mA
Number of Circuits	8 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Clock Speed	60 MHz
Number of Bits	8 Bit
Polarity	Non-Inverting
Input Capacitance	10 pF
Number of Inputs	8 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
	expand all
Size-Length	24.33 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

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Product Description

The CD74HC273E is an octal high speed CMOS D-type Flip-flop with reset and direct clear input. It is manufactured with silicon-gate CMOS technology. It possesses the low power consumption of standard CMOS integrated circuits. Information at the D inputs transferred to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CP) and a common reset (MR\\). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.
Common clock and asynchronous master reset
Positive edge triggering
Buffered inputs
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS input compatibility
10 LSTTL Load standard outputs
15 LSTTL Load bus driver outputs

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