CD74HCT74M - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HCT74M
Manufacturer

TI
ChipWorker Part#

CW5638125
Category

Flip Flop IC
Package

SOIC-14
Description

Flip-Flop, 74HCT74, D, 35ns, 50MHz, SOIC
Documentation

Datasheet

CD74HCT74M Global Supplier

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CD74HCT74M Specifications

Attribute	Attribute Value

Part Number	CD74HCT74M
Manufacturer	TI
ChipWorker Part#	CW5638125
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	SOIC-14
Frequency	50 MHz
Digital Logic Level	CMOS
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Number of Outputs	1 Output
Output Current	4 mA
Number of Circuits	2 Circuit
Number of Positions	14 Position
Clock Speed	50 MHz
Number of Bits	2 Bit
Polarity	Non-Inverting, Inverting
Number of Gates	2 Gate
Input Capacitance	10 pF
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Size-Length	8.65 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17

Product Description

The CD74HCT74M is a dual positive-edge-triggered high speed CMOS D-type Flip-flop with set and reset. It utilizes silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop has independent DATA, SET\, RESET\ and CLOCK inputs and Q and Q\ outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET\ and RESET\ are independent of the clock and are accomplished by a low level at the appropriate input. The HCT logic family is functionally as well as pin compatible with the standard LS logic family.
Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
Asynchronous set and reset
Complementary outputs
Buffered inputs
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS input compatibility
10 LSTTL Load standard outputs
15 LSTTL Load bus driver outputs
Green product and no Sb/Br

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