IR2103SPBF - Infineon

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

IR2103SPBF
Manufacturer

Infineon
ChipWorker Part#

CW10795746
Category

FET Driver
Package

SOIC-8
Description

MOSFET DRVR 600V 0.36A 2Out Hi/Lo Side Half Brdg Inv/Non-Inv 8Pin SOIC
Documentation

Datasheet

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IR2103SPBF Specifications

Attribute	Attribute Value

Part Number	IR2103SPBF
Manufacturer	Infineon
ChipWorker Part#	CW10795746
Category	FET Driver
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	10.0V (min)
Rise/Fall Time	100ns, 50ns
Number of Outputs	2 Output
Output Voltage	620 V
Output Current	270 mA
Number of Channels	2 Channel
Number of Positions	8 Position
Power Dissipation	625 mW
Fall Time (Max)	90 ns
Fall Time (Max)	170 ns
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	625 mW
Supply Voltage	10V ~ 20V
Supply Voltage (Max)	20 V
Supply Voltage (Min)	10 V
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Size-Length	5 mm
Size-Width	4 mm
Size-Height	1.5 mm
Operating Temperature	-40℃ ~ 150℃ (TJ)
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The IR2103SPBF is a high voltage high speed power MOSFET and IGBT Half-Bridge Driver with dependent high and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600V.
Floating channel designed for bootstrap operation
Tolerant to negative transient voltage (dV/dt immune)
Under-voltage lockout
3.3, 5 and 15V Logic input compatible
Cross-conduction prevention logic
Matched propagation delay for both channels
Internal set dead-time
High-side output in phase with HIN input
Low-side output out of phase with LIN input

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