MC100LVEP111FAG - ON Semiconductor

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

MC100LVEP111FAG
Manufacturer

ON Semiconductor
ChipWorker Part#

CW7183835
Category

Clock Buffer, Driver, PLL IC
Package

LQFP-32
Description

2.5V / 3.3V 2:1:10 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer, 32 LEAD LQFP 7x7, 0.8P, 250-JTRAY
Documentation

Datasheet

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MC100LVEP111FAG Specifications

Attribute	Attribute Value

Part Number	MC100LVEP111FAG
Manufacturer	ON Semiconductor
ChipWorker Part#	CW7183835
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	32 Pin
Case/Package	LQFP-32
Frequency	3 GHz
Supply Voltage (DC)	2.38V (min)
Halogen Free Status	Halogen Free
Number of Outputs	10 Output
Supply Current	90.0 mA
Number of Circuits	1 Circuit
Number of Positions	32 Position
Input Current	90 mA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.375V ~ 3.8V
Supply Voltage (Max)	3.8 V
Supply Voltage (Min)	2.375 V
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Size-Length	7 mm
Size-Width	7 mm
Size-Height	1.45 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	EAR99

Product Description

The MC100LVEP111FAG is a 2:1:10 low skew Differential Driver designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP111 is operating under PECL conditions. The LVEP111 specifically guarantees low output-to-output skew. Optimal design, layout and processing minimize skew within a device and from device to device. To ensure tightest skew, both sides of differential outputs identically terminate into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. It can be operated from a positive VCC supply in PECL mode. This allows the LVEP111 to be used for high performance clock distribution in 3.3 or 2.5V systems. Single-ended CLK input operation is limited to a VCC>=3V in PECL mode or VEE -3V in NECL mode when using VBB.
<1ps RMS Jitter
VBB output contains temperature compensation
Open input default state
LVDS Input compatible
Fully compatible with MC100EP111
430ps Typical propagation delay

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