SN65MLVD201D - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65MLVD201D
Manufacturer

TI
ChipWorker Part#

CW6903469
Category

Interface IC, Interface Controller
Package

SOIC-8
Description

Line Transmitter/Receiver 1TR 1 Transceiver 1 Receiver 8Pin SOIC Tube
Documentation

Datasheet

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SN65MLVD201D Specifications

Attribute	Attribute Value

Part Number	SN65MLVD201D
Manufacturer	TI
ChipWorker Part#	CW6903469
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SOIC-8
Supply Voltage (DC)	3.00V (min)
Supply Current	24 mA
Number of Positions	8 Position
Input Current	24.0 mA
Power Dissipation	725 W
Data Rate	200 Mbps
Input Current (Min)	10 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	725 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	5A991.b.1

Product Description

The SN65MLVD201D is a Half-duplex Transceiver optimized to operate at signaling rates up to 200Mbps. All parts comply with the multipoint low-voltage differential signaling M-LVDS standard TIA/EIA-899. This circuit is similar to their TIA/EIA-644 standard compliant LVDS counterparts with added features to address multipoint applications. The driver output has been designed to support multipoint buses presenting loads as low as 30R and incorporates controlled transition times to allow for stubs off of the backbone transmission line. This device has type-1 and type-2 receivers that detect the bus state with as little as 50mV of differential input voltage over a common-mode voltage range of -1 to 3.4V. The type-1 receivers exhibit 25mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus and other faults conditions.
Controlled driver output voltage transition times for improved signal quality
Bus pins high impedance when disabled or VCC
Meets or exceeds the M-LVDS standard TIA/EIA-899 for multipoint data interchange
M-LVDS Bus power up/down glitch free
Green product and no Sb/Br

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