SN74ALVCH32973KR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74ALVCH32973KR
Manufacturer

TI
ChipWorker Part#

CW47174743
Category

Logic Controller, Logic IC
Package

BGA-96
Description

16Bit Bus Transceiver and Transparent D-Type Latch with 8Independent Buffers 96-LFBGA -40℃ to 85℃
Documentation

Datasheet

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SN74ALVCH32973KR Specifications

Attribute	Attribute Value

Part Number	SN74ALVCH32973KR
Manufacturer	TI
ChipWorker Part#	CW47174743
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	96 Pin
Case/Package	BGA-96
Supply Voltage (DC)	1.65V ~ 3.60V
Number of Outputs	40 Output
Number of Circuits	2 Circuit
Number of Channels	16 Channel
Number of Positions	96 Position
Number of Bits	16 Bit
Propagation Delay Max (tpd)	3.00 ns
Static Current	60.0 µA
Output Current Drive	-1.00 mA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.65 V
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Size-Height	0.95 mm
Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	Non-Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

This device contains eight independent noninverting buffers and a 16-bit noninverting bus transceiver and D-type latch, designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH32973 is particularly suitable for demultiplexing an address/data bus into a dedicated address bus and dedicated data bus. The device is used where there is asynchronous bidirectional communication between the A and B data bus, and the address signals are latched and buffered on the Q bus. The control-function implementation minimizes external timing requirements.
This device can be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit transceiver, and one 16-bit latch. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The transceiver output-enable (TOE)\ input can be used to disable the transceivers so that the A and B buses effectively are isolated.
When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE)\ input can be used to place the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, LOE\ and TOE\ should be tied to VCC through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of the drivers.
The eight independent noninverting buffers perform the Boolean function Y = D, and are independent of the state of DIR, TOE\, LE, and LOE\\\\.
The A and B I/Os, and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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