SN74LVC1G374YZPR ,Flip Flop IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Popularity Score

63 points

Part No

SN74LVC1G374YZPR
Manufacturer

TI
ChipWorker Part#

CW17428161
Category

Flip Flop IC
Package

DSBGA-6
Description

Flip Flop D-Type Pos-Edge 3-ST 1Element 6Pin DSBGA T/R
Documentation

Datasheet
Ships from

Moscow
Наличие

In Stock
Estimated Price

$ 0.57

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SN74LVC1G374YZPR Specifications

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Attribute	Attribute Value

Part Number	SN74LVC1G374YZPR
Manufacturer	TI
ChipWorker Part#	CW17428161
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	6 Pin
Case/Package	DSBGA-6
Supply Voltage (DC)	5.00 V
Number of Outputs	1 Output
Number of Circuits	1 Circuit
Number of Channels	1 Channel
Clock Speed	175 MHz
Number of Bits	1 Bit
Propagation Delay Max (tpd)	3.00 ns
Polarity	Non-Inverting
Number of Gates	1 Gate
Input Capacitance	3 pF
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Length	1.4 mm
Size-Width	0.9 mm
Size-Height	0.3 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free

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Product Description

This single D-type latch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input.
A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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