SN74LVC2G125DCUT ,Logic Controller, Logic IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

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116 points

Part No

SN74LVC2G125DCUT
Manufacturer

TI
ChipWorker Part#

CW18972015
Category

Logic Controller, Logic IC
Package

VSSOP-8
Description

Buffer/Line Driver 2CH Non-Inverting 3-ST CMOS 8Pin VSSOP T/R
Documentation

Datasheet
Ships from

Moscow
Наличие

In Stock
Estimated Price

$ 0.23

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SN74LVC2G125DCUT Specifications

Consulting Engineer >>

Attribute	Attribute Value

Part Number	SN74LVC2G125DCUT
Manufacturer	TI
ChipWorker Part#	CW18972015
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	VSSOP-8
Supply Voltage (DC)	1.65V (min)
Number of Outputs	2 Output
Number of Channels	2 Channel
Number of Positions	8 Position
Number of Bits	2 Bit
Propagation Delay Max (tpd)	3.70 ns
Number of Gates	2 Gate
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
	expand all
Size-Length	2.3 mm
Size-Width	2 mm
Size-Height	0.85 mm
Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	Yes
REACH SVHC Compliance Edition	2015/06/15

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Product Description

The SN74LVC2G125DCUT is a dual Bus Buffer Gate designed for 1.65 to 5.5V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This device contains dual buffer gate device with output enable control and performs the Boolean function Y = A. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver.
IOFF Supports live insertion, partial-power-down mode and back-drive protection
Allows down voltage translation
Can be used as a down translator to translate inputs from 5.5V down to the VCC level
Inputs accept voltages to 5.5V
Latch-up performance exceeds 250mA per JESD 17
4.3ns at 3.3V Propagation delay (tpd)
10µA ICC Low power consumption
±24mA Output drive at 3.3 V
<0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
>2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)
Green product and no Sb/Br

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