ADN4667ARUZ - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

ADN4667ARUZ
Manufacturer

ADI
ChipWorker Part#

CW1038145
Category

Interface IC, Interface Controller
Package

TSSOP-16
Description

Analog Devices ADN4667ARUZ, LVDS Transmitter Quad CMOS/ TTL LVDS, 3 → 3.6V, 16Pin, TSSOP
Documentation

Datasheet

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ADN4667ARUZ Specifications

Attribute	Attribute Value

Part Number	ADN4667ARUZ
Manufacturer	ADI
ChipWorker Part#	CW1038145
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Voltage (DC)	3.00V (min)
Supply Current	30 mA
Number of Positions	16 Position
Power Dissipation	10 W
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	10 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	5.1 mm
Size-Width	4.5 mm
Size-Height	1.05 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/12/17
ECCN Code	5A991.b.4

Product Description

The ADN4667ARUZ is a quad CMOS low voltage differential signalling (LVDS) Line Driver offering data rates of over 400Mbps (200MHz) and ultralow power consumption. It features a flow-through pin-out for easy PCB layout and separation of input and output signals. The device accepts low voltage TTL/CMOS logic signals and converts it to a differential current output of typically ±3.1mA for driving a transmission medium such as a twisted pair cable. The transmitted signal develops a differential voltage of typically ±310mV across a termination resistor at the receiving end. This is converted back to a TTL/CMOS logic level by an LVDS receiver. The ADN4667 also offers active high and active low enable/disable inputs (EN and EN). These inputs control all four drivers and turn off the current outputs in the disabled state to reduce the quiescent power consumption to typically 10mW.
Flow-through pin-out simplifies PCB layout
300ps Typical differential skew
400ps Maximum differential skew
1.7ns Maximum propagation delay
Low power dissipation
Interoperable with existing 5V LVDS receivers
High impedance on LVDS outputs on power-down

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