CD74HC423M - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HC423M
Manufacturer

TI
ChipWorker Part#

CW20073519
Category

Flip Flop IC
Package

SOIC-16
Description

Monostable Multivibrator Dual -55℃ 125℃ 16Pin SOIC Tube
Documentation

Datasheet

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CD74HC423M Specifications

Attribute	Attribute Value

Part Number	CD74HC423M
Manufacturer	TI
ChipWorker Part#	CW20073519
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC-16
Supply Voltage (DC)	2.00V (min)
Output Current	5.2 mA
Number of Circuits	2 Circuit
Number of Channels	2 Channel
Number of Positions	16 Position
Number of Bits	2 Bit
Number of Gates	2 Gate
Rise Time	400 ns
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	9.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
ECCN Code	EAR99

Product Description

The CD74HC423M is a dual CMOS retriggerable Monostable Multivibrator with RESET. It is retriggerable and differs only in that the 123 types can be triggered by a negative to positive RESET pulse, whereas the 423 types do not have this feature. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and CX provides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the A\ and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses. Once triggered, the output pulse width may be extended by retriggering inputs A\ and B. The output pulse can be terminated by a low level on the RESET (R) pin. Trailing edge triggering (A\\) and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A\, B and R\\) must be terminated high or low.
Overriding RESET terminates output pulse
Triggering from the leading or trailing edge
Q and Q\ Buffered outputs
Separate resets
Wide range of output-pulse widths
Schmitt trigger on both A\ and B inputs
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
Direct LSTTL input logic compatibility
CMOS input compatibility
Green product and no Sb/Br

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