CDC3RL02YFPR ,Clock Buffer, Driver, PLL IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Popularity Score

163 points

Part No

CDC3RL02YFPR
Manufacturer

TI
ChipWorker Part#

CW2639896
Category

Clock Buffer, Driver, PLL IC
Package

DSBGA-8
Description

Clock Buffer 2Out 1IN 1:1 8Pin DSBGA T/R
Documentation

Datasheet
Ships from

Moscow
Наличие

In Stock
Estimated Price

$ 1.29

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CDC3RL02YFPR Specifications

Consulting Engineer >>

Attribute	Attribute Value

Part Number	CDC3RL02YFPR
Manufacturer	TI
ChipWorker Part#	CW2639896
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	DSBGA-8
Frequency	52 MHz
Supply Voltage (DC)	1.80 V
Number of Outputs	2 Output
Supply Current	50.0 mA
Number of Circuits	1 Circuit
Number of Positions	8 Position
Duty Cycle	55 %
Maximum Duty Cycle	55 %
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	0.3V ~ 1.8V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2.3 V
	expand all
Size-Length	1.59 mm
Size-Width	0.79 mm
Size-Height	0.31 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

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Product Description

The CDC3RL02YFPR is a two-channel clock Fan-out Buffer ideal for portable end-equipment, such as mobile phones, that requiring clock buffering with minimal additive phase noise and fan-out capabilities. It buffers a single master clock, such as a temperature compensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each of which enable a single clock output. The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an AC coupling capacitor. The smallest acceptable sine wave is a 0.3V signal (peak-to-peak). It has been designed to offer minimal channel-to-channel skew, additive output jitter and additive phase noise. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity and minimizes ringing caused by signal reflections on the clock distribution lines.
Low additive noise
0.37ps RMS Output Jitter
Limited output slew rate for EMI reduction
Adaptive output stage controls reflection
ESD Performance exceeds JESD 22
Green product and no Sb/Br

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