DM3730CBP - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

DM3730CBP
Manufacturer

TI
ChipWorker Part#

CW22649203
Category

DSP, Digital Signal Processor
Package

FCBGA-515
Description

DSP Fixed-Point 32Bit 800MHz/800MHz 2000MIPS 515Pin POP-FCBGA Tray
Documentation

Datasheet

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DM3730CBP Specifications

Attribute	Attribute Value

Part Number	DM3730CBP
Manufacturer	TI
ChipWorker Part#	CW22649203
Category	DSP, Digital Signal Processor
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	515 Pin
Case/Package	FCBGA-515
Frequency	1 GHz
Number of Positions	515 Position
Clock Speed	660 MHz
RAM Memory Size	64 KB
Number of Bits	32 Bit
Number of UARTs	4 UART
Number of Inputs and Outputs	188 IO
Operating Temperature (Max)	90 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage (Max)	1.2 V
Supply Voltage (Min)	1.08 V
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Size-Height	0.5 mm
Operating Temperature	0℃ ~ 90℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	5A992.c

Product Description

* DM3730, DM3725 Digital Media Processors: * Compatible with OMAP™ 3 Architecture * ARM® microprocessor (MPU) Subsystem * Up to 1-GHz ARM® Cortex™-A8 Core, Also supports 300, 600, and 800-MHz * NEON SIMD Coprocessor * High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem * Up to 800-MHz TMS320C64x+™ DSP Core * Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) * Video Hardware Accelerators * POWER SGX™ Graphics Accelerator (DM3730 only) * Tile Based Acrchitecture Delivering up to 20 MPoly/sec * Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality * Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 * Fine Grained Task Switching, Load Balancing, and Power Management * Programmable High Quality Image Anti-Aliasing * Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core * Eight Highly Independent Functional Units * Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle * Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-bit Multiplies (16-Bit Results) per Clock Cycle * Load-Store Architecture With Non-Aligned Support * 64 32-Bit General-Purpose Registers * Instruction Packing Reduces Code Size * All Instructions Conditional * Additional C64x+™ Enhancements * Protected Mode Operation * Expectations Support for Error Detection and Program Redirection * Hardware Support for Modulo Loop Operation * C64x+TM L1/L2 Memory Architecture * * *

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