S25FS128SDSNFI101 - Cypress Semiconductor

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

S25FS128SDSNFI101
Manufacturer

Cypress Semiconductor
ChipWorker Part#

CW71803344
Category

Memory Chip
Package

WDFN-8
Description

NOR Flash Serial-SPI 1.8V 128Mbit 128M x 1Bit 8Pin WSON Tube
Documentation

Datasheet

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S25FS128SDSNFI101 Specifications

Attribute	Attribute Value

Part Number	S25FS128SDSNFI101
Manufacturer	Cypress Semiconductor
ChipWorker Part#	CW71803344
Category	Memory Chip
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	WDFN-8
Supply Voltage (DC)	1.70V (min)
Number of Positions	8 Position
Clock Speed	80 MHz
Memory Size	16000000 B
Access Time(Max)	8 ns
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.7V ~ 2V
Supply Voltage (Max)	2 V
Supply Voltage (Min)	1.7 V
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Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Unknown
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status
REACH SVHC Compliance Edition	2015/12/17

Product Description

The S25FS128SDSNFI101 is a 128MB MirrorBit® Flash Non-Volatile Memory with 1.8V single supply and CMOS I/O serial peripheral interface with multi-I/O. Traditional SPI 1-bit serial input and output is supported as well as optional 2-bit and 4-bit wide quad I/O or quad peripheral interface serial commands. This multiple width interface is called SPI multi-I/O or MIO. In addition, there are double data rate read commands for QIO and QPI that transfer address and read data on both edges of the clock. The FS-S eclipse architecture features a page programming buffer that allows up to 512 bytes to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. By using S25FS-S family device at the higher clock rates supported, with quad or DDR quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically.
SPI Clock polarity and phase modes 0 and 3
Serial command set and footprint compatible with S25FL-A, S25FL-K and S25FL-P SPI families
Multi I/O command set and footprint compatible with S25FL-P and S25FL-S SPI family
Serial flash discoverable parameters and common flash interface, for configuration information
Program suspend and resume
Erase suspend and resume
Erase status evaluation
100000 Program-erase cycles on any sector minimum
20 Years data retention typical
Individual sector protection controlled by boot code or password
Spansion 65nm MirrorBit technology with Eclipse™ Architecture

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