TPS51200DRCT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

TPS51200DRCT
Manufacturer

TI
ChipWorker Part#

CW122400
Category

Voltage Regulator
Package

VSON-10
Description

Single Channel LDO Sink/Source DDR Termination Regulator LDO Regulator Neg/Pos -0.3V to 6V 3A 10Pin VSON EP T/R
Documentation

Datasheet

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TPS51200DRCT Specifications

Attribute	Attribute Value

Part Number	TPS51200DRCT
Manufacturer	TI
ChipWorker Part#	CW122400
Category	Voltage Regulator
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	10 Pin
Case/Package	VSON-10
Power Rating	1.92 W
Number of Outputs	1 Output
Output Voltage	1.25 V
Output Current	3 A
Number of Positions	10 Position
Input Current	1 µA
Power Dissipation	1920 W
Quiescent Current	500 µA
Output Capacitor Type	Ceramic
voltage rating	15 mV
Number of Regulated Outputs	1 Output
Input Voltage (Max)	3.5 V
Input Voltage (Min)	2.375 V
Output Current (Max)	3 A
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1920 mW
Supply Voltage (Max)	3.5 V
Supply Voltage (Min)	2.375 V
Input Voltage	2.38V ~ 3.5V
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Size-Length	3 mm
Size-Width	3 mm
Size-Height	0.9 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

The TPS51200DRCT is a sink/source Double Data Rate (DDR) Termination Regulator, specifically designed for low input voltage, low-noise systems where space is a key consideration. The TPS51200DRCT maintains a fast transient response and only requires a minimum output capacitance of 20µF. The TPS51200DRCT supports a remote sensing function and all power requirements for DDR, DDR2, DDR3 and low power DDR3/DDR4 VTT bus termination. In addition, the TPS51200DRCT provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.
1.1 to 3.5V VLDOIN Voltage range
Sink/source termination regulator includes droop compensation
Requires minimum output capacitance of 20µF (typically 3 x 10µF MLCCs)
PGOOD to monitor output regulation
EN Input
REFIN Input allows for flexible input tracking either directly or through resistor divider
Remote sensing (VOSNS)
±10mA Buffered reference (REFOUT)
Built-in soft start, UVLO and OCL
Thermal shutdown
Meets DDR, DDR2 JEDEC specifications, supports DDR3 and low-power DDR3/DDR4 VTT applications
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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