SN65LVDS047PW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS047PW
Manufacturer

TI
ChipWorker Part#

CW15637729
Category

Interface IC, Interface Controller
Package

TSSOP-16
Description

TEXAS INSTRUMENTS SN65LVDS047PW Differential Line Driver IC, 400Mbps Data Rate, 8kV ESD, 3V to 3.6V, TSSOP-18
Documentation

Datasheet

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SN65LVDS047PW Specifications

Attribute	Attribute Value

Part Number	SN65LVDS047PW
Manufacturer	TI
ChipWorker Part#	CW15637729
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Voltage (DC)	3.00V (min)
Number of Positions	18 Position
Power Dissipation	774 mW
Data Rate	400 Mbps
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	950 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDS047PW is a quad differential Line Driver implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds and allow operation with a 3.3V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247mV into a 100R load when enabled. The intended application of this device and signaling technique is for point-to-point and multi-drop baseband data transmission over controlled impedance media of approximately 100R. The transmission media may be printed-circuit board traces, backplanes or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment and other system characteristics.
Flow-through pin-out simplifies PCB layout
High impedance on LVDS outputs on power-down
Conforms to TIA/EIA-644 LVDS standard
>400Mbps (200MHz) Signalling rate
300ps Maximum differential skew
1.8ns Typical propagation delay time
3.3V Power supply design
±350mV Differential signalling
Green product and no Sb/Br

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